pericom semiconductor corp. www.pericom.com page 1 of 1 5/21/2009 pci express ? and pcie ? are registered trademarks of pci-sig ? www.pcisig.org | usb ? is a trademark of usb implementers forum, inc pericom ? is a registered trademark of pericom semiconductor corp. product: pci express ? (pcie ? ) to usb ? 2.0 swidge part numbers: PI7C9X442SL product description the PI7C9X442SL pci express ? to usb ? 2.0 swidge is designed to meet the latest low-power, lead (pb)-free and green system requirements. the PI7C9X442SL is a cost-effective solution that can be implemented in systems such as volume servers, embedded systems, motherboards, laptops, docking stations, peripherals, pc add-in cards and other footprint sensitive platforms requiring multiple usb host connections. the PI7C9X442SL provides one x1 upstream pcie port, two x1 downstream pcie ports, and up to 4 usb 2.0 host controller ports. the PI7C9X442SL provides users the flexibility to expand or fan-out from a wide range of i/o bridges such as ioh, pch, ich, embedded mcu and other application specific ics. industry specifications compliance pcie base specification, revision 1.1 pcie cem specification, revision 1.1 pci-to-pci bridge architecture spec., rev 1.2 advanced configuration power interface (acpi) specification universal serial bus (usb) 2.0 compliant (1.5/12/480 mbps) universal serial bus(usb) ehci 1.0a/ohci 1.0 compliant system management (sm) bus, 1.0 compliant pci express packet switch features one x1 pcie 1.1 upstream port and two x1 pcie 1.1 downstream ports supports ?cut-through?(default) as well as ?store and forward? mode for packet switching 150 ns typical latency for packet routed through switch without blocking non-blocking full-wired switching capability at 16 gbps when 3 ports plus 4 usb 2.0 ports are all enabled advanced power saving o empty downstream ports are set to idle state to minimize power consumption link power management o supports l0, l0s, l1, l2, l2/l3ready and l3 link power state o active state power management for l0s and l1 state o pme# support in l2 state device state power management o supports d0, d3hot and d3cold device power state o 3.3v aux power support in d3cold power state port arbitration: round robin (rr), weighted rr and time-based weighted rr supports up to 256-byte maximum payload size programmable driver current and de-emphasis level at each pcie port reliability, availability and serviceability usb 2.0 host controller features usb root hub with 4 (max.) downstream facing ports which are shared by ohci and ehci host controllers all usb downstream facing ports can handle high speed (480 mbps), full speed (12 mbps) and low speed (1.5 mbps) transactions pci multi-function device c onsists of two ohci host controllers for full speed/low speed signaling and one ehci host controller for high speed signaling usb host controller operational registers directed-mapped to pci general features strapped pins configurable with optional eeprom or smbus interface support extended commercial temperature range 0 o to 85 o 128-pin lqfp 14mm x 14mm package applications notebook pc motherboard notebook docking stations embedded system volume servers multifunction printers consumer electronics peripheral pc add-in card/ express card industrial pc telecom/networking soho router PI7C9X442SL root complex host cpu x1 pcie x1 pcie x1 pcie usb 2.0 usb 2.0 usb 2.0 usb 2.0 pcie endpoint pcie endpoint PI7C9X442SL ? block diagram order information part number package pb-free & green temperature PI7C9X442SLfde 128 lqfp yes 0 o c to 85 o c PI7C9X442SLevb board evaluation kit for PI7C9X442SL
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